1. Field of the Invention
Embodiments of the present invention relate generally to three-dimensional (3D) graphics processing, and, more specifically, to on-chip anti-alias resolve in a cache tiling architecture.
2. Description of the Related Art
Many graphics processing tasks generate intermediate data, which is data that is generated and used during the execution of a graphics processing task, but is not the final data output for the graphics processing task. One type of graphics processing task that generates intermediate data is multi-sample anti-aliasing, which is a particular type of anti-aliasing technique in which multiple color samples are generated for each screen pixel. The multiple color samples associated with each screen pixel are then resolved to generate a blended color value for each screen pixel. In multi-sample anti-aliasing, the multiple samples are deemed intermediate data because the samples are not the final output of the graphics processing task; rather, the blended color values for the screen pixels constitute the final output.
Some graphics subsystems implement a tiling architecture in which a render target is subdivided into cache tiles. Work received by such a graphics subsystem is rearranged such that the work is processed in cache tile order. In other words, work associated with a first cache is processed first, then work associated with a second cache tile is processed, then work associated with a third cache tile, and so forth. In some implementations, data associated with cache tiles is maintained in an on-chip cache memory while the cache tile is being processed, which reduces the amount of traffic between the on-chip cache and the frame buffer. This approach in turn reduces memory bandwidth utilization and associated power consumption. Also, in some implementations, the architecture includes multiple processing entities that operate in concert to process each cache tile. Each processing entity is assigned a portion of each cache tile and performs processing operations associated with that portion.
Several challenges exist with respect to performing anti-aliasing in an architecture that implements cache tiling and includes multiple processing entities. For example, the multiple processing entities need to be configured to manage data dependencies that are associated with the multi-sample anti-aliasing operation. Although these data dependencies exist in a graphics subsystem with only one processing entity, performing multi-sample anti-aliasing with multiple processing entities that cooperate to render each cache tile complicates the steps that need to be taken to manage these data dependencies, because data dependencies may exist across processing entities.
Another challenging aspect of processing multi-sample anti-aliasing operations in a graphics subsystem that includes multiple processing entities that implement a cache tiling architecture is managing data flow between the cache memory that stores the cache tiles and an external memory such as a frame buffer. As described above, intermediate data, such as the sample data is only needed during the multi-sample anti-aliasing operation, and is not the final output of such operation. Such intermediate data need not be written out from the cache memory to the frame buffer. Writing such intermediate data out to the frame buffer would unnecessarily consume memory bandwidth and power.
As the foregoing illustrates, what is needed in the art are techniques for managing intermediate data associated with anti-aliasing, while also managing data dependencies between the operations in the anti-aliasing task.